1. Field of the Invention
The present invention relates, most generally, to semiconductor structures, and more particularly to interconnect structures.
2. Description of the Related Art
With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been proposed and are being used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements. In order to achieve high-speed performance, dimensions of transistors have been shrinking. Also, multi-layer interconnect structures have been proposed and/or used to provide desired operational speeds of transistors.
FIG. 1A is a schematic cross-sectional view showing a traditional interconnect structure.
Referring to FIG. 1A, a low-k dielectric layer 110 is formed over a substrate 100. Conductive structures 120 are formed within the low-k dielectric layer 110. The conductive structures 120 and the low-k dielectric layer 110 have a substantially level surface. Then, an etch stop layer 130, a glue layer 140 and another low-k dielectric layer 150 are sequentially formed over the dielectric layer 110. Conductive structures 160 are then formed within the dielectric layer 150, the glue layer 140 and the etch stop layer 130.
The etch stop layer 130 and the glue layer 140 are dielectric layers having dielectric constants higher than those of the low-k dielectric layers 110 and 150. The presence of the etch stop layer 130 and the glue layer 140 within the interconnect structure may increase the inter or intra parasitic capacitances between adjacent conductive structures 120 and/or 160.
In order to solve the issue of parasitic capacitances, some structures without the etch stop layer 130 and/or the glue layer 140 (shown in FIG. 1A) are provided. Referring to FIG. 1B, the interconnect structure includes the low-k dielectric layer 110 formed over the substrate 100. The conductive structures 120 are formed within the low-k dielectric layer 110. The conductive structures 120 and the low-k dielectric layer 110 have a substantially level surface. Without forming the etch stop layer 130 and the glue layer 140 (shown in FIG. 1A), the low-k dielectric layer 150 is formed over the dielectric layer 110. The conductive structures 160 are then formed within the dielectric layer 150, contacting the conductive structures 120. Accordingly, the inter or intra parasitic capacitances within the interconnect structure can be desirably reduced.
Based on the foregoing, methods and structures for forming dies with multi-layer interconnect structures are desired.